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Features
* Servo Processing Unit (SPU), Using Dedicated 16-bit Instruction Cycle AVR(R) RISC * * * * * * * * * * * * * * * * * * * * *
Cores (3), Giving 120 MIPS Maximum Processing Power with 40 MHz SYSCLK SPU Includes 17 x 17 Single-clock Cycle MAC On-chip Debugger Monitor for Program Development (OCDM) 8K Words Program RAM 4K Bytes Data RAM On-chip Clock Frequency Synthesizer with Output Clock Buffers for AT78C1501 Controller On-chip S/H and WCS Timing State Machine (TSM) for Conversion of Focus, Tracking and SUM Signals 10-bit 1.2 sec ADC with six-channel MUX Synchronized ADC Conversions with SPU Interrupt Service Routine Three Fast 10-bit 500 nsec (rise time) DACs for Servo Loops and Adjustments Three 8-bit DACs for Offset Adjustment and Spin Loop Bandgap ADC and DAC Midpoint Reference Outputs SPU Implemented Spindle Speed Control Spindle Interface Logic and Hardware Support for Both CAV and CLV Spindle Control Modes Eight General Purpose I/O Pins SPU Servo Control of Focus, Fine Track, Coarse Track and Tray Load Motors High-speed Track Counter for Accurate High-speed Track Counts (1.4 MHz when used with AT78C1503 Read Channel) Lower Power Operations with 3.3V Core and 5V Tolerant I/Os 8-bit Data and 14-bit Address Controller/Microprocessor Interface 3-pin Universal Serial Port Interface to Program Read Channel and Power Devices Power Management On-chip UART to Access OCDM Unit
DVD/CD Servo AT78C1502
Description
The Atmel AT78C1502 high-performance servo controller fully integrates all of the control and demodulation functions for DVD and CD, optical/mechanical systems. Packaged in 128-lead TQFP and fabricated in 0.35 micron CMOS, the device operates on a 3.3V logic/analog supply and provides 5V tolerance for digital I/O. An AVRbased Servo Processing Unit (SPU) embedded in the device provides programmable control of spindle speed, coarse and fine tracking, focus, sled, draw motor and tilt. The three parallel programmable AVR microcontrollers in the SPU are the heart of the system, offering a range of servo sample rates. With only a 40 MHz system clock, 120 MIPS of processing power is provided. Real-time notch filters can also be calculated. Fast 10-bit DACs provide real-time control of servo loops and other system adjustments. A universal serial port and many general purpose I/Os are provided. AVR0 is the master AVR of the three microcontrolloers, communicating with AVR1, AVR2 and the ARMTDMI in the AT78C1501 interface controller and to the AT78C1503 read channel. An On-Chip Debugger Monitor (OCDM) is offered to enable programmers to easily observe theeffect of changes to code on each AVR. System-level evaluation boards are available with development code in both C and native code for basic operation of all servos. Simple changes to the code allow any mechadeck to be interfaced to the AT78C1502.
Rev. 2050A-DVD-07/02
1
Figure 1. DVD System Block Diagram
DRAM
Flash
AT78C1502 Servo Control System
Power Drivers
Sled
AT78C1501 ATAPI I/F Controller DBM ECC SRAM ARM7TDMI
Focus
Spindle
AT78C1503 Read Channel
Laser
AT78C1504 Laser Power Controller
T08XX Laser Amp
AT78C1507 Read Channel Adj.
AT78C1505 Pre-amp
2
AT78C1502
2050A-DVD-07/02
AT78C1502
Figure 2. Pin-out
128 DGND D0 D1 D2 D3 DVDD D4 D5 D6 D7 DGND WRB RDB CSB CINT CINTAQK TESTMODE DVDD OCDM TM4 TM3 TM2 TM1 TM0 DGND MRST WG IDF JTRIG LHP DVDD TOK BCA TZC MIRR FOK HD1,2 DGND 1
DGND A13 A12 A11 A10 A9 A8 A7 A6 A5 DVDD A4 A3 A2 A1 A0 DGND XIN XOUT CLK2 CLK1 DVDD N/C FSFILT FSIS DGND 103 102
AT78C1502 128-lead TQFP
38 39 64
65
DGND N/C CAP GPP7 GPP6 GPP5 GPP4 GPP3 GPP2 GPP1 GPP0 DVDD SPCLK BEMF TXD RXD SCLK SDATA SDEN2 SDEN1 SDEN0 DGND AGND FDAC FDACREF FINDAC FINDACREF AVDD CRSDAC CRSDACREF DAC1 DAC0 N/C AVDD 2VBG VBG N/C AGND
DGND HD3,4 CNTRST SINT SF ADCSTR AVDD MUXOUT AIN6 AIN5 MTRK MTRKFB AGND LPS LPSFB FCS FCSFB AVDD SUM SUMFB RDSZ RDSZFB N/C N/C ADCREF AGND
3
2050A-DVD-07/02
External Pin Definition
P = Power or ground, B = Bidirectional, I = Digital Input, O = Digital Output. AI = Analog Input, AO = Analog Output. Table 1. External Pin Definition
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Symbol DGND D0 D1 D2 D3 DVDD D4 D5 D6 D7 DGND WRB RDB CSB CINT CINTACK TMODE DVDD OCDM_ENAB TM4/MUX4 TM3/MUX3 TM2/MUX2 TM1/MUX1 TM0/MUX0 DGND MRST WG IDF JTRIG LHP DVDD TOK BCA Type P B B B B P B B B B P I I I I O I P I I I I I I P I I I I I P I I Description Digital Ground Data Bus Data Bus Data Bus Data Bus Digital VDD Data Bus Data Bus Data Bus Data Bus Digital Ground Chip Write Select Chip Read Select Chip Select Input Interrupt Input from Controller Controller Interrupt Acknowledge Test Mode Select Input - Active-low Digital VDD On-chip Debug/Monitor Mode Test Mode Select Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Test Mode Select Input/MUX Output Digital Ground Master Reset Input Write Gate Input from Controller I/D Field Input from Controller Jump Trigger Input from Controller Laser High Power Input from Controller Digital Power Track OK Input from Read Channel Burst Cutting Area (Defect Flag Input)
4
AT78C1502
2050A-DVD-07/02
AT78C1502
Table 1. External Pin Definition (Continued)
Pin # 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 Symbol TZC MIRR FOK HD1,2 DGND DGND HD3,4 CNTRST SINT SF ADCSTR AVDD MUX_OUT AIN6 AIN5 MTRK MTRKFB AGND LPS LPS FCS FCSF AVDD SUM SUMF RDSZ RDSZF N/C N/C ADCREF AGND AGND N/C VBG 2VBG AVDD AO AO P AI P P Type I I I I P P I I O O O P AO AI AI AI AI P AI AI AI AI P AI AI AI AI Description Track Zero Crossing from Read Channel Mirror Input from Read Channel Focus OK Signal from Read Channel Header 1, 2 Input from Read Channel Digital Ground Digital Ground Header 3, 4 Input from Read Channel TSM Counter Reset Signal Servo Interrupt Output to Controller Servo Fault Output to Controller ADC Strobe Output from TSM Analog VDD Analog MUX Output Analog Input to MUX Analog Input to MUX MUXed Track Track/Hold Input MUXed Track Filter Input Analog Ground Lens Position Sensor Track/Hold Input Lens Position Sensor Filter Input Focus Error Signal Track/Hold Input Focus Error Signal Filter Input Analog VDD Slow Sum Track/Hold Input Slow Sum Input Filter Read Size Input Read Size Input Filter No Connect No Connect Reference I/P for ADC Analog GND Analog GND No Connect Bandgap Output Voltage 2*Bandgap Output Voltage Analog VDD
5
2050A-DVD-07/02
Table 1. External Pin Definition (Continued)
Pin # 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 Symbol N/C DAC0 DAC1 CRSDAC CRSDACREF AVDD FINDAC FINDACREF FDAC FDACREF AGND DGND SDEN0 SDEN1 SDEN2 SDATA SCLK RXD TXD BEMF SPCLK DVDD GPP0 GPP1 GPP2 GPP3 GPP4 GPP5 GPP6 GPP7 CAP N/C DGND DGND FSIS FSFILT P P I I AO AO AO AI P AO AI AO AI P P O O O B O I O I O P B B B B B B B B I Type Description No Connect 8-bit Offset DAC Output 8-bit Offset DAC Output 10-bit Coarse Tracking DAC Coarse DAC Ref Input Analog VDD 10-bit Fine Tracking DAC Fine DAC Ref Input 10-bit Focus DAC Focus DAC Ref Input Analog GND Digital GND Serial Data Enable #0 Serial Data Enable #1 Serial Data Enable #2 Serial Data Serial CLK UART Receive Data Input UART Transmit Data Output Back EMF Zero Crossing Input Spin Pseudo Register Output Digital VDD General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit General Purpose I/O Port Bit External Event Capture No Connect Digital Ground Digital Ground Frequency Synthesizer Iset Frequency Synthesizer Filter
6
AT78C1502
2050A-DVD-07/02
AT78C1502
Table 1. External Pin Definition (Continued)
Pin # 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Symbol N/C DVDD CLK1 CLK2 XOUT XIN DGND A0 A1 A2 A3 A4 DVDD A5 A6 A7 A8 A9 A10 A11 A12 A13 DGND P O O O I P I I I I I P I I I I I I I I I P Type Description No Connect Digital VDD Clock 1 Output Clock 1 Output Crystal Out Connection Crystal Input/Clock Input Digital Ground Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Digital VDD Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Address Bus Input Digital GND
7
2050A-DVD-07/02
Figure 3. Block Diagram
RD TD
A (13:0) D (7:0) WRB RDB CSB Controller Interface (CIF)
Program Space and Data Space Dual-Port RAM
UART
Serial Interface Port (SIP)
SDENA2 SDENA1 SDENA0 SDATA SCLK
CINT CINTACK SINT SF ADCREF MUXOUT
Interrupt Control Logic (ICL)
Servo Processing Unit (SPU)
General Purpose Port (GPP)
DAC Output Block (DOB)
GPP (7:0)
CRSDAC FINDAC FDAC DAC1 DAC0 CNTRST CAP FOK IDF WG JTRIG LHP BCA HD1,2 HD3,4
MTRK FCS SUM RDSZ LPS AIN4 AIN5 Track Hold & Filter (THF) Timing State Machine (TSM)
MUX & ADC (MAD)
Servo Input Block (SIB)
Band Gap Ref
Frequency Synthesizer (FQS)
Clock Osc and Distribution (COD)
Track Counter (TRCNT)
TOK TZC MIRR
Spindle Control Logic (SCL)
SPCLK BEMF
2.5V
1.25V
ISET
FILT
8
AT78C1502
2050A-DVD-07/02
CLK1 CLK2 XIN XOUT
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) and AVR (R) are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2050A-DVD-07/02

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